Yield enhancement for WSI array processors using two-and-half-track switches

J. S N Jean, H. C. Fu, Sun-Yuan Kung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

The enhancement of fabrication yield for arrays of large numbers of processors is considered. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, it is possible to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.

Original languageEnglish (US)
Title of host publication1990 Proc Int Conf Wafer Scale Integr
EditorsJoe Brewer, Michael J. Little
PublisherPubl by IEEE
Pages243-250
Number of pages8
ISBN (Print)0818690135
StatePublished - Jan 1 1990
Externally publishedYes
Event1990 Proceedings - International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: Jan 23 1990Jan 25 1990

Other

Other1990 Proceedings - International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period1/23/901/25/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Jean, J. S. N., Fu, H. C., & Kung, S-Y. (1990). Yield enhancement for WSI array processors using two-and-half-track switches. In J. Brewer, & M. J. Little (Eds.), 1990 Proc Int Conf Wafer Scale Integr (pp. 243-250). Publ by IEEE.