Yield enhancement for WSI array processors using two-and-half-track switches

J. S N Jean; H. C. Fu; Sun-Yuan Kung

Yield enhancement for WSI array processors using two-and-half-track switches

J. S N Jean, H. C. Fu, Sun-Yuan Kung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The enhancement of fabrication yield for arrays of large numbers of processors is considered. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, it is possible to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.

Original language	English (US)
Title of host publication	1990 Proc Int Conf Wafer Scale Integr
Editors	Joe Brewer, Michael J. Little
Publisher	Publ by IEEE
Pages	243-250
Number of pages	8
ISBN (Print)	0818690135
State	Published - Jan 1 1990
Externally published	Yes
Event	1990 Proceedings - International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: Jan 23 1990 → Jan 25 1990

Other

Other	1990 Proceedings - International Conference on Wafer Scale Integration
City	San Francisco, CA, USA
Period	1/23/90 → 1/25/90

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

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title = "Yield enhancement for WSI array processors using two-and-half-track switches",

abstract = "The enhancement of fabrication yield for arrays of large numbers of processors is considered. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, it is possible to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.",

author = "Jean, {J. S N} and Fu, {H. C.} and Sun-Yuan Kung",

year = "1990",

month = jan,

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editor = "Joe Brewer and Little, {Michael J.}",

booktitle = "1990 Proc Int Conf Wafer Scale Integr",

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note = "1990 Proceedings - International Conference on Wafer Scale Integration ; Conference date: 23-01-1990 Through 25-01-1990",

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AU - Jean, J. S N

AU - Fu, H. C.

AU - Kung, Sun-Yuan

PY - 1990/1/1

Y1 - 1990/1/1

N2 - The enhancement of fabrication yield for arrays of large numbers of processors is considered. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, it is possible to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.

AB - The enhancement of fabrication yield for arrays of large numbers of processors is considered. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, it is possible to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.

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UR - http://www.scopus.com/inward/citedby.url?scp=0025250998&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025250998

SN - 0818690135

SP - 243

EP - 250

BT - 1990 Proc Int Conf Wafer Scale Integr

A2 - Brewer, Joe

A2 - Little, Michael J.

PB - Publ by IEEE

T2 - 1990 Proceedings - International Conference on Wafer Scale Integration

Y2 - 23 January 1990 through 25 January 1990

ER -

Yield enhancement for WSI array processors using two-and-half-track switches

Abstract

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All Science Journal Classification (ASJC) codes

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