By incorporating certain structured global interconnections into systolic or wavefront arrays, it is possible to improve the speed performance significantly. Specifically, the authors consider a highly parallel architecture, the wavefront array processor, and enhance its overall performance using a global communication scheme. Efficient algorithms implementable on this enhanced architecture are discussed. A testbed array computer system based on commercially available VLSI chips such as transputers for signal processing applications is being developed.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - Dec 1 1985|
All Science Journal Classification (ASJC) codes