WAVEFRONT ARRAY PROCESSOR AND BEYOND.

S. Y. Kung, V. K.Prasanna Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

By incorporating certain structured global interconnections into systolic or wavefront arrays, it is possible to improve the speed performance significantly. Specifically, the authors consider a highly parallel architecture, the wavefront array processor, and enhance its overall performance using a global communication scheme. Efficient algorithms implementable on this enhanced architecture are discussed. A testbed array computer system based on commercially available VLSI chips such as transputers for signal processing applications is being developed.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages176-179
Number of pages4
ISBN (Print)0818606428
StatePublished - Dec 1 1985
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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