Voltage and frequency control with adaptive reaction time in multiple-clock-domain processors

Qiang Wu, Philo Juang, Margaret Rose Martonosi, Douglas W. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

44 Scopus citations

Abstract

Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clock domain (MCD) processors. Most existing online DVFS schemes for MCD processors use a fixed time interval between possible voltage /frequency changes. The downside to this approach is that the interval boundaries are predetermined and independent of workload changes. Thus, they can be late in responding to large, severe activity swings. In this work, we propose an alternative online DVFS scheme in which the reaction time is self-tuned and adaptive to application and work-load changes. In addition to designing such a scheme, we model the proposed DVFS control and use the derived model in a formal stability analysis. The obtained analytical insight is then used to guide and improve the design in terms of stability margin and control effectiveness. We evaluate our DVFS scheme through cycle-accurate simulation over a wide set of MediaBench and SPEC2000 benchmarks. Compared to the best-known prior fixed-interval DVFS schemes for MCD processors, the proposed DVFS scheme has a simpler decision process, which leads to smaller and cheaper hardware. Our scheme has achieved significant energy savings over all studied benchmarks (19% energy savings with 3% performance degradation on average, which is close to the best results from existing fixed-interval DVFS schemes). For a group of applications with fast workload variations, our scheme outperforms existing fixed-interval DVFS schemes significantly due to its adaptive nature. Overall, we feel the proposed adaptive online DVFS scheme is an effective and promising alternative to existing fixed-interval DVFS schemes. Designers may choose the new scheme for processors with limited hardware budget, or if the anticipated work-load behavior is variable. In addition, the modeling and analysis techniques in this work serve as examples of using stability analysis in other aspects of high-performance CPU design and control.

Original languageEnglish (US)
Title of host publicationProceedings - 11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005
Pages178-189
Number of pages12
DOIs
StatePublished - Dec 12 2005
Event11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005 - San Francisco, CA, United States
Duration: Feb 12 2005Feb 16 2005

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005
CountryUnited States
CitySan Francisco, CA
Period2/12/052/16/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Wu, Q., Juang, P., Martonosi, M. R., & Clark, D. W. (2005). Voltage and frequency control with adaptive reaction time in multiple-clock-domain processors. In Proceedings - 11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005 (pp. 178-189). (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2005.43