VLSI systolic array implementation of a staged decoder for BCM signals

G. Caire, J. Ventura-Traveset, J. Murphy, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).

Original languageEnglish (US)
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages139-149
Number of pages11
ISBN (Electronic)0780308115, 9780780308114
DOIs
StatePublished - Jan 1 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: Oct 28 1992Oct 30 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992

Conference

Conference6th IEEE Workshop on VLSI Signal Processing
CountryUnited States
CityLos Angeles
Period10/28/9210/30/92

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • Cite this

    Caire, G., Ventura-Traveset, J., Murphy, J., & Kung, S. Y. (1992). VLSI systolic array implementation of a staged decoder for BCM signals. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 139-149). [641046] (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641046