VLSI systolic array implementation of a staged decoder for BCM signals

G. Caire; J. Ventura-Traveset; J. Murphy; S. Y. Kung

doi:10.1109/VLSISP.1992.641046

VLSI systolic array implementation of a staged decoder for BCM signals

G. Caire, J. Ventura-Traveset, J. Murphy, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).

Original language	English (US)
Title of host publication	Workshop on VLSI Signal Processing 1992
Editors	Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	139-149
Number of pages	11
ISBN (Electronic)	0780308115, 9780780308114
DOIs	https://doi.org/10.1109/VLSISP.1992.641046
State	Published - Jan 1 1992
Event	6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States Duration: Oct 28 1992 → Oct 30 1992

Publication series

Name	Workshop on VLSI Signal Processing 1992

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing
Country	United States
City	Los Angeles
Period	10/28/92 → 10/30/92

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/VLSISP.1992.641046

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Caire, G., Ventura-Traveset, J., Murphy, J., & Kung, S. Y. (1992). VLSI systolic array implementation of a staged decoder for BCM signals. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 139-149). [641046] (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641046

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author = "G. Caire and J. Ventura-Traveset and J. Murphy and Kung, {S. Y.}",

year = "1992",

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Caire, G, Ventura-Traveset, J, Murphy, J & Kung, SY 1992, VLSI systolic array implementation of a staged decoder for BCM signals. in W Przytula, K Yao, R Jain & J Rabaey (eds), Workshop on VLSI Signal Processing 1992., 641046, Workshop on VLSI Signal Processing 1992, Institute of Electrical and Electronics Engineers Inc., pp. 139-149, 6th IEEE Workshop on VLSI Signal Processing, Los Angeles, United States, 10/28/92. https://doi.org/10.1109/VLSISP.1992.641046

VLSI systolic array implementation of a staged decoder for BCM signals. / Caire, G.; Ventura-Traveset, J.; Murphy, J.; Kung, S. Y.

Workshop on VLSI Signal Processing 1992. ed. / Wojtek Przytula; Kung Yao; Rajeev Jain; Jan Rabaey. Institute of Electrical and Electronics Engineers Inc., 1992. p. 139-149 641046 (Workshop on VLSI Signal Processing 1992).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Caire G, Ventura-Traveset J, Murphy J, Kung SY. VLSI systolic array implementation of a staged decoder for BCM signals. In Przytula W, Yao K, Jain R, Rabaey J, editors, Workshop on VLSI Signal Processing 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 139-149. 641046. (Workshop on VLSI Signal Processing 1992). https://doi.org/10.1109/VLSISP.1992.641046