VLSI systolic array implementation of a staged decoder for BCM signals

G. Caire; J. Ventura-Traveset; J. Murphy; S. Y. Kung

doi:10.1109/VLSISP.1992.641046

VLSI systolic array implementation of a staged decoder for BCM signals

G. Caire, J. Ventura-Traveset, J. Murphy, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).

Original language	English (US)
Title of host publication	Workshop on VLSI Signal Processing 1992
Editors	Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	139-149
Number of pages	11
ISBN (Electronic)	0780308115, 9780780308114
DOIs	https://doi.org/10.1109/VLSISP.1992.641046
State	Published - 1992
Event	6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States Duration: Oct 28 1992 → Oct 30 1992

Publication series

Name	Workshop on VLSI Signal Processing 1992

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing
Country/Territory	United States
City	Los Angeles
Period	10/28/92 → 10/30/92

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering
Applied Mathematics

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10.1109/VLSISP.1992.641046

Cite this

Caire, G., Ventura-Traveset, J., Murphy, J., & Kung, S. Y. (1992). VLSI systolic array implementation of a staged decoder for BCM signals. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 139-149). [641046] (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641046

@inproceedings{5d83894a1f92485296d15d3162e0fde4,

title = "VLSI systolic array implementation of a staged decoder for BCM signals",

abstract = "This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).",

author = "G. Caire and J. Ventura-Traveset and J. Murphy and Kung, {S. Y.}",

note = "Funding Information: The authors wish to thank Prof. Biglieri for having provided the manuscript of [6]. Mr.Caire, Mr.Ventura-Traveset and Captain Murphy thank respectively AEI (Italy), “La Caixa” (Spain) and the United States Army fellowships for funding their research at Princeton University. Publisher Copyright: {\textcopyright} 1992 IEEE.; 6th IEEE Workshop on VLSI Signal Processing ; Conference date: 28-10-1992 Through 30-10-1992",

year = "1992",

doi = "10.1109/VLSISP.1992.641046",

language = "English (US)",

series = "Workshop on VLSI Signal Processing 1992",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "139--149",

editor = "Wojtek Przytula and Kung Yao and Rajeev Jain and Jan Rabaey",

booktitle = "Workshop on VLSI Signal Processing 1992",

address = "United States",

}

Caire, G, Ventura-Traveset, J, Murphy, J & Kung, SY 1992, VLSI systolic array implementation of a staged decoder for BCM signals. in W Przytula, K Yao, R Jain & J Rabaey (eds), Workshop on VLSI Signal Processing 1992., 641046, Workshop on VLSI Signal Processing 1992, Institute of Electrical and Electronics Engineers Inc., pp. 139-149, 6th IEEE Workshop on VLSI Signal Processing, Los Angeles, United States, 10/28/92. https://doi.org/10.1109/VLSISP.1992.641046

VLSI systolic array implementation of a staged decoder for BCM signals. / Caire, G.; Ventura-Traveset, J.; Murphy, J. et al.

Workshop on VLSI Signal Processing 1992. ed. / Wojtek Przytula; Kung Yao; Rajeev Jain; Jan Rabaey. Institute of Electrical and Electronics Engineers Inc., 1992. p. 139-149 641046 (Workshop on VLSI Signal Processing 1992).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - VLSI systolic array implementation of a staged decoder for BCM signals

AU - Caire, G.

AU - Ventura-Traveset, J.

AU - Murphy, J.

AU - Kung, S. Y.

N1 - Funding Information: The authors wish to thank Prof. Biglieri for having provided the manuscript of [6]. Mr.Caire, Mr.Ventura-Traveset and Captain Murphy thank respectively AEI (Italy), “La Caixa” (Spain) and the United States Army fellowships for funding their research at Princeton University. Publisher Copyright: © 1992 IEEE.

PY - 1992

Y1 - 1992

N2 - This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).

AB - This article deals with the design and VLSI Systolic Array hardware implementation of a Staged Decoder suitable for decoding Block-Coded-Modulated signals (BCM).

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U2 - 10.1109/VLSISP.1992.641046

DO - 10.1109/VLSISP.1992.641046

M3 - Conference contribution

AN - SCOPUS:85068142980

T3 - Workshop on VLSI Signal Processing 1992

SP - 139

EP - 149

BT - Workshop on VLSI Signal Processing 1992

A2 - Przytula, Wojtek

A2 - Yao, Kung

A2 - Jain, Rajeev

A2 - Rabaey, Jan

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Workshop on VLSI Signal Processing

Y2 - 28 October 1992 through 30 October 1992

ER -

VLSI systolic array implementation of a staged decoder for BCM signals

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