Abstract
The key issues in designing an algorithm-oriented array processor are addressed in this tutorial. The author discusses how to express the parallelism and description of the space-time activities associated with a parallel algorithm, how to systematically derive a VLSI array hardware design, and how to apply the methodology to image/vision processing applications. The applications include 2-D convolution for edge detection, rank order filter for noise removal and artificial neural nets for associative classification.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Publisher | Publ by IEEE |
Pages | 313-320 |
Number of pages | 8 |
Volume | 1 |
ISBN (Print) | 9517212399 |
State | Published - Dec 1 1988 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials