VLSI array processors: Designs and applications

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


The key issues in designing an algorithm-oriented array processor are addressed in this tutorial. The author discusses how to express the parallelism and description of the space-time activities associated with a parallel algorithm, how to systematically derive a VLSI array hardware design, and how to apply the methodology to image/vision processing applications. The applications include 2-D convolution for edge detection, rank order filter for noise removal and artificial neural nets for associative classification.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Number of pages8
ISBN (Print)9517212399
StatePublished - 1988

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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