Virtual Intermediate Bus CPU Voltage Regulator

Yenan Chen, Ping Wang, Hsin Cheng, Gregory Szczeszynski, Stephen Allen, David M. Giuliano, Minjie Chen

Research output: Contribution to journalArticlepeer-review

50 Scopus citations


This article presents a merged two-stage 48-V-to-1-V point-of-load (PoL) architecture with a 24-V virtual intermediate bus (VIB) for CPU voltage regulator applications. The VIB-PoL architecture includes two power conversion stages linked by a 24-V VIB with a significant voltage ripple. The first stage is a 2:1 interleaved charge pump, which converts 48 to 24 V. The second stage comprises multiple interleaved four-level series-capacitor buck modules with coupled inductors, converting 24 V to regulated 1 V with an equivalent voltage conversion ratio of 6:1. The VIB-PoL architecture achieves high efficiency and high power density by reducing the power conversion stress of both stages and eliminating the intermediate bus capacitors. A 48-V-to-1-V 640-A CPU voltage regulator with a peak power stage efficiency of 95.2% (93.3%, including gate driver loss), a full-load efficiency of 84.4% (83.1%, including gate driver loss), and a power density of 463 W/in3 (at 1-V output with liquid cooling) is built and tested to demonstrate the VIB-PoL architecture.

Original languageEnglish (US)
Pages (from-to)6883-6898
Number of pages16
JournalIEEE Transactions on Power Electronics
Issue number6
StatePublished - Jun 1 2022

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


  • Coupled inductor
  • dcâ dc
  • point of load (PoL)
  • switched-capacitor (SC) converter
  • voltage regulator


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