Verification of asynchronous interface circuits with bounded wire delays

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence under various modes of operation.

Original languageEnglish (US)
Pages (from-to)161-182
Number of pages22
JournalJournal of VLSI Signal Processing
Issue number1-2
StatePublished - Feb 1 1994

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering


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