Verification of asynchronous interface circuits with bounded wire delays

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table, under the fundamental mode of operation. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design
PublisherPubl by IEEE
Pages188-195
Number of pages8
ISBN (Print)0818630108
StatePublished - Dec 1 1992
Externally publishedYes
EventIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
Duration: Nov 8 1992Nov 12 1992

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
CitySanta Clara, CA, USA
Period11/8/9211/12/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Devadas, S., Keutzer, K., Malik, S., & Wang, A. (1992). Verification of asynchronous interface circuits with bounded wire delays. In IEEE/ACM International Conference on Computer-Aided Design (pp. 188-195). (IEEE/ACM International Conference on Computer-Aided Design). Publ by IEEE.