Variability-tolerant register-transfer level synthesis

Anish Muttreja, Srivaths Ravi, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.

Original languageEnglish (US)
Title of host publicationProceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Number of pages8
StatePublished - 2008
Event21st International Conference on VLSI Design, VLSI DESIGN 2008 - Hyderabad, India
Duration: Jan 4 2008Jan 8 2008

Publication series

NameProceedings of the IEEE International Frequency Control Symposium and Exposition


Other21st International Conference on VLSI Design, VLSI DESIGN 2008

All Science Journal Classification (ASJC) codes

  • General Engineering


Dive into the research topics of 'Variability-tolerant register-transfer level synthesis'. Together they form a unique fingerprint.

Cite this