TY - GEN
T1 - Variability-tolerant register-transfer level synthesis
AU - Muttreja, Anish
AU - Ravi, Srivaths
AU - Jha, Niraj K.
PY - 2008
Y1 - 2008
N2 - Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.
AB - Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.
UR - http://www.scopus.com/inward/record.url?scp=47649117371&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47649117371&partnerID=8YFLogxK
U2 - 10.1109/VLSI.2008.114
DO - 10.1109/VLSI.2008.114
M3 - Conference contribution
AN - SCOPUS:47649117371
SN - 0769530834
SN - 9780769530833
T3 - Proceedings of the IEEE International Frequency Control Symposium and Exposition
SP - 621
EP - 628
BT - Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
T2 - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Y2 - 4 January 2008 through 8 January 2008
ER -