Using register-transfer paths in code generation for heterogeneous memory-register architectures

Guido Araujo, Sharad Malik, Mike Tien Chien Lee

Research output: Contribution to journalConference article

29 Scopus citations

Abstract

In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer paths, that can be used for efficiently dismantling basic block DA Gs (Directed Acyclic Graphs) into expression trees. This approach builds on recent results which report optimal code generation algorithm for expression trees for these architectures. This technique has been implemented and experimentally validated for the TMS320C25, a popular fixed point DSP processor. The results show that good code quality can be obtained using the proposed technique. An analysis of the type of DAGs found in the DSPstone benchmark programs reveals that the majority of basic blocks in this benchmark set are expression trees and leaf DAGs. This leads to our claim that tree based algorithms, like the one described in this paper, should be the technique of choice for basic block code generation with heterogeneous memory-register architectures.

Original languageEnglish (US)
Pages (from-to)591-596
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - Jan 1 1996
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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