Using reconfigurable hardware to customize memory hierarchies

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Over the past decade or more, processor speeds have increased much more quickly than memory speeds. As a result, a large, and still increasing, processor-memory performance gap has formed. Many significant applications suffer from substantial memory bottlenecks, and their memory performance problems are often either too unusual or extreme to be mitigated by cache memories along. Such specialized performance 'bugs' require specialized solutions, but it is impossible to provide case-by-case memory hierarchies or caching strategies on general-purpose computers. We have investigated the potential of implementing mechanisms like victim caches and prefetch buffers in reconfigurable hardware to improve application memory behavior. Based on technology and commercial trends, our simulation-based studies use a forward-looking model in which configurable logic is located on the CPU chip. Given such assumptions, our results show that the flexibility of being able to specialize configurable hardware to an application's memory referencing behavior more than balances the slightly slower response times of configurable memory hierarchy structures. For our three applications, small, specialized memory hierarchy additions such as victim caches and prefetch buffers can reduce miss rates substantially and can drop total execution times for these programs to between 60 and 80% of their original execution times. Our results also indicate that different memory specializations may be most effective for each application; this highlights the usefulness of configurable memory hierarchies that are specialized on a per-application basis.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsJohn Schewel, Peter M. Athanas, V.Michael Jr. Bove, John Watson
Pages237-248
Number of pages12
Volume2914
StatePublished - Dec 1 1996
EventHigh-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic - Boston, MA, USA
Duration: Nov 20 1996Nov 21 1996

Other

OtherHigh-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
CityBoston, MA, USA
Period11/20/9611/21/96

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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    Zhong, P., & Martonosi, M. R. (1996). Using reconfigurable hardware to customize memory hierarchies. In J. Schewel, P. M. Athanas, V. M. J. Bove, & J. Watson (Eds.), Proceedings of SPIE - The International Society for Optical Engineering (Vol. 2914, pp. 237-248)