Using delayed addition techniques to accelerate integer and floating-point calculations in configurable hardware

This paper proposes and evaluates an approach for improving the performance of arithmetic calculations via delayed addition. Our approach employs the idea used in Wallace trees to delay addition until the end of a repeated calculation such as accumulation or dot-product; this effectively removes carry propagation overhead from the calculation's critical path. We present integer and floating-point designs that use this technique. Our pipelined integer multiply-accumulate (MAC) design is based on a fairly traditional multiplier design, but -with delayed addition as well. This design achieves a 37MHz clock rate on an XC4036XL-2 FPGA. Next, we present a 32-bit floating-point accumulator based on delayed addition. Here delayed addition requires a novel alignment technique that decouples the incoming operands from the accumulated result. A conservative version of this design achieves a 33 MHz clock rate. Finally, we also present a more aggressive 32-bit floating-point accumulator design that achieves a 66MHz clock rate. These designs demonstrate the utility of delayed addition for accelerating FPGA calculations in both the integer and floating-point domains.