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Usage-based RTL subsetting for hardware accelerators
Qinhan Tan
,
Aarti Gupta
,
Sharad Malik
Computer Science
Electrical and Computer Engineering
Princeton Institute for Computational Science and Engineering
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
1
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Scopus citations
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Keyphrases
Hardware Accelerator
100%
Subsetting
100%
Usage-based
100%
NVDLA
66%
Information Flow
33%
Multiple Levels
33%
Under-approximation
33%
Hardware Complexity
33%
Large Set
33%
Individual Use
33%
Program Synthesis
33%
Effective Algorithm
33%
High Cost
33%
Power Performance
33%
Taint Analysis
33%
Function Set
33%
Performance Efficiency
33%
Computation Cost
33%
Synthesis Problem
33%
Temporal Properties
33%
Computing Platform
33%
Number of Gates
33%
RTL Design
33%
Hardware Verification
33%
Verification Complexity
33%
NVIDIA
33%
Convolution Function
33%
Co-verification
33%
Hyperproperties
33%
Deep Learning Accelerator
33%
Power Verification
33%
Algorithm-based
33%
Over 50
33%
Property Checking
33%
Silicon Area
33%
Domain-specific Accelerator
33%
Computer Science
Hardware Accelerator
100%
Approximation (Algorithm)
100%
Use Case
100%
Program Synthesis
100%
Open Source
100%
Case Study
100%
temporal property
100%
Computing Platform
100%
Computation Cost
100%
Emerging Application
100%
Synthesis Problem
100%
Deep Learning Method
100%
Convolution
100%