Unsatisfiability based efficient design for testability solution for register-transfer level circuits

Keyphrases

• Register Transfer Level 100%
• Design for Testability 100%
• Unsatisfiability 100%
• Test Case Generation 30%
• Test Vector 20%
• Test Sequence 20%
• Gate Level 20%
• Greedy Algorithm 10%
• Order of Magnitude 10%
• Recent Advances 10%
• CPU Time 10%
• Area Overhead 10%
• Satisfiability Solvers 10%
• Fault Coverage 10%
• Low Area 10%
• Module Level 10%
• Proposed Design 10%
• Generation Tools 10%
• Accurate Method 10%
• Sequential Test 10%
• Test Case Generator 10%
• Single Run 10%

Computer Science

• Register-Transfer Level 100%
• Experimental Result 12%
• Greedy Algorithm 12%
• Test Generation 12%
• Fault Coverage 12%

Engineering

• Circuit Variable 10%