Abstract
Summary form only given. A universal digital VLSI design is proposed for implementing a wide variety of artificial neural networks. A programmable systolic array is presented based on a unified iterative neural network model, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant for a universal simulation tool and neurocomputer architecture, which can implement a variety of algorithms in both the retrieving and the learning phases of ANNs, e.g., single-layer feedback networks, competitive learning networks, multilayer feedforward networks, and stochastic neural networks. A fault-tolerance approach and partitioning scheme for large or nonhomogeneous networks are also proposed.
Original language | English (US) |
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Pages | 614 |
Number of pages | 1 |
State | Published - 1989 |
Event | IJCNN International Joint Conference on Neural Networks - Washington, DC, USA Duration: Jun 18 1989 → Jun 22 1989 |
Other
Other | IJCNN International Joint Conference on Neural Networks |
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City | Washington, DC, USA |
Period | 6/18/89 → 6/22/89 |
All Science Journal Classification (ASJC) codes
- General Engineering