Universal digital VLSI design for neural networks

H. C. Fu, J. N. Hwang, S. Y. Kung, W. D. Mao, J. A. Vlontzos

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


Summary form only given. A universal digital VLSI design is proposed for implementing a wide variety of artificial neural networks. A programmable systolic array is presented based on a unified iterative neural network model, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant for a universal simulation tool and neurocomputer architecture, which can implement a variety of algorithms in both the retrieving and the learning phases of ANNs, e.g., single-layer feedback networks, competitive learning networks, multilayer feedforward networks, and stochastic neural networks. A fault-tolerance approach and partitioning scheme for large or nonhomogeneous networks are also proposed.

Original languageEnglish (US)
Number of pages1
StatePublished - 1989
EventIJCNN International Joint Conference on Neural Networks - Washington, DC, USA
Duration: Jun 18 1989Jun 22 1989


OtherIJCNN International Joint Conference on Neural Networks
CityWashington, DC, USA

All Science Journal Classification (ASJC) codes

  • General Engineering


Dive into the research topics of 'Universal digital VLSI design for neural networks'. Together they form a unique fingerprint.

Cite this