Universal digital VLSI design for neural networks

H. C. Fu, J. N. Hwang, Sun-Yuan Kung, W. D. Mao, J. A. Vlontzos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Summary form only given. A universal digital VLSI design is proposed for implementing a wide variety of artificial neural networks. A programmable systolic array is presented based on a unified iterative neural network model, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant for a universal simulation tool and neurocomputer architecture, which can implement a variety of algorithms in both the retrieving and the learning phases of ANNs, e.g., single-layer feedback networks, competitive learning networks, multilayer feedforward networks, and stochastic neural networks. A fault-tolerance approach and partitioning scheme for large or nonhomogeneous networks are also proposed.

Original languageEnglish (US)
Title of host publicationIJCNN Int Jt Conf Neural Network
Editors Anon
PublisherPubl by IEEE
Number of pages1
StatePublished - Dec 1 1989
EventIJCNN International Joint Conference on Neural Networks - Washington, DC, USA
Duration: Jun 18 1989Jun 22 1989

Other

OtherIJCNN International Joint Conference on Neural Networks
CityWashington, DC, USA
Period6/18/896/22/89

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Fu, H. C., Hwang, J. N., Kung, S-Y., Mao, W. D., & Vlontzos, J. A. (1989). Universal digital VLSI design for neural networks. In Anon (Ed.), IJCNN Int Jt Conf Neural Network Publ by IEEE.