Universal digital VLSI design for neural networks

Summary form only given. A universal digital VLSI design is proposed for implementing a wide variety of artificial neural networks. A programmable systolic array is presented based on a unified iterative neural network model, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant for a universal simulation tool and neurocomputer architecture, which can implement a variety of algorithms in both the retrieving and the learning phases of ANNs, e.g., single-layer feedback networks, competitive learning networks, multilayer feedforward networks, and stochastic neural networks. A fault-tolerance approach and partitioning scheme for large or nonhomogeneous networks are also proposed.