Ultra-low-leakage, robust FinFET SRAM design using multiparameter asymmetric FinFETs

Abdullah Guler, Niraj K. Jha

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58x while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22x leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells.

Original languageEnglish (US)
Article number26
JournalACM Journal on Emerging Technologies in Computing Systems
Issue number2
StatePublished - Nov 2016

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


  • FinFET
  • Leakage power
  • Multiparameter asymmetry
  • SRAM design


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