Ultra-low-leakage and high-performance logic circuit design using multiparameter asymmetric FinFETs

Engineering

• Logic Design 100%
• Gate Circuit 100%
• Logic Gate 50%
• Performance Degradation 25%
• Physical Parameter 25%
• Metal-Oxide-Semiconductor Field-Effect Transistor 25%
• Field-Effect Transistor 25%
• Delay Constraint 25%
• Oxide Thickness 25%
• Fin Thickness 25%
• Supply Voltage 25%
• Gate Length 25%
• Gate Oxide 25%
• Moore's Law 25%
• Process Variation 25%
• Transistor 25%

Keyphrases

• Logic Circuit Design 100%