Recently, multigate field-effect transistors have started replacing traditional planar MOSFETs to keep pace with Moore's Law in deep submicron technology. Among different multigate transistors, FinFETs have become the preferred choice of the semiconductor industry owing to low fabrication cost, superior performance, lower leakage, and design flexibility. The back and front gates of a FinFET can either be shorted or remain independent, leading to two modes of operation: Shorted-Gate (SG) and Independent-Gate (IG). For a given mode of operation, the physical parameters of the FinFET can either be symmetric or asymmetric in nature. In this article, for the first time, we analyze multiparameter asymmetric SG FinFETs and illustrate their potential for implementing logic gates and circuits that are both ultra-low-leakage and high-performance simultaneously. We restrict this work to SG devices because IG FinFETs (symmetric/asymmetric) suffer from severely degraded on-current, which makes them unattractive for high-performance designs. We first compare head-to-head all viable single- and multiparameter symmetric/asymmetric SG FinFETs. Among all such FinFETs, the traditional SG (which are symmetric in nature), Asymmetric Workfunction Shorted-Gate (AWSG), and Asymmetric Workfunction-Underlap Shorted-Gate (AWUSG) FinFETs show the most promise. We characterize these devices under process variations in gate length (LG), fin thickness (TSI), gate-oxide thickness (TOX), gate underlap (LUN), and gate-workfunction (ΦG) as well as supply voltage (VDD) variations, followed by a gate-level leakage/delay analysis at different temperatures. Although AWSG FinFETs consume very low leakage power, they do suffer from performance degradation relative to SG FinFETs. Similarly, our study reveals that no other single-parameter asymmetric FinFET provides a good combination of low-power and high-performance design. We show that gates/circuits based on AWUSG FinFETs are faster, yet consume much less leakage power and less area than gates/circuits based on traditional SG FinFETs. We observe 53.4% (30.2%) maximum (average) reduction in total power at temperature T = 348K while meeting the same delay constraint, with 14.2% (13.5%) reduction in area for AWUSG circuits relative to SG circuits. At T = 373K, we see 68.6% (46.9%) maximum (average) reduction in total power.
|Original language||English (US)|
|Journal||ACM Journal on Emerging Technologies in Computing Systems|
|State||Published - Mar 2016|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Multiparameter asymmetry