TY - JOUR
T1 - Ultra-High Density Monolithic 3-D FinFET SRAM with Enhanced Read Stability
AU - Bhattacharya, Debajit
AU - Jha, Niraj K.
N1 - Funding Information:
his work was supported by the NSF under Grant No. CCF-1318603. This paper was recommended by Associate Editor X. Zhang.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2016/8
Y1 - 2016/8
N2 - FinFETs have begun replacing planar CMOS in the post-22 nm era because of their superior short-channel behavior. Though FinFETs will continue to extend Moore's law for the next few technology generations, 3-D vertical integration will enable more-than-Moore density increase by increasing the transistor count that can be accommodated in an IC package. Compared to conventional through-silicon-via (TSV)-based 3-D integration methods, monolithic 3-D integration enables higher density of transistors owing to the much smaller monolithic inter-tier vias (MIVs). In this paper, for the first time, we explore the design possibilities for FinFET-based ultra-high density monolithic 3-D SRAMs. These SRAMs can exploit the height difference between the n- and p-FinFETs placed in two different layers to improve overall SRAM stability. We investigate several 6T and 8T monolithic 3-D FinFET SRAM bitcells and evaluate their dc and transient stability/performance metrics, taking process variations into account. We propose a new 8T 3-D SRAM bitcell that shows a 39% improvement in read stability and 25% improvement in footprint area without affecting writeability, when compared with the conventional 2-D 6T SRAM bitcell.
AB - FinFETs have begun replacing planar CMOS in the post-22 nm era because of their superior short-channel behavior. Though FinFETs will continue to extend Moore's law for the next few technology generations, 3-D vertical integration will enable more-than-Moore density increase by increasing the transistor count that can be accommodated in an IC package. Compared to conventional through-silicon-via (TSV)-based 3-D integration methods, monolithic 3-D integration enables higher density of transistors owing to the much smaller monolithic inter-tier vias (MIVs). In this paper, for the first time, we explore the design possibilities for FinFET-based ultra-high density monolithic 3-D SRAMs. These SRAMs can exploit the height difference between the n- and p-FinFETs placed in two different layers to improve overall SRAM stability. We investigate several 6T and 8T monolithic 3-D FinFET SRAM bitcells and evaluate their dc and transient stability/performance metrics, taking process variations into account. We propose a new 8T 3-D SRAM bitcell that shows a 39% improvement in read stability and 25% improvement in footprint area without affecting writeability, when compared with the conventional 2-D 6T SRAM bitcell.
KW - FinFET
KW - SRAM
KW - TCAD
KW - monolithic 3-D integration
KW - noise margin
KW - process variation
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U2 - 10.1109/TCSI.2016.2565641
DO - 10.1109/TCSI.2016.2565641
M3 - Article
AN - SCOPUS:84979085539
SN - 1549-8328
VL - 63
SP - 1176
EP - 1187
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 8
M1 - 7508447
ER -