TRANSISTENCY MODELS: MEMORY ORDERING AT THE HARDWARE–OS INTERFACE

Daniel Lustig; Geet Sethi; Abhishek Bhattacharjee; Margaret Rose Martonosi

doi:10.1109/MM.2017.265090228

TRANSISTENCY MODELS: MEMORY ORDERING AT THE HARDWARE–OS INTERFACE

Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Rose Martonosi

Research output: Contribution to journal › Article › peer-review

Abstract

THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM’S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.

Original language	English (US)
Pages (from-to)	88-97
Number of pages	10
Journal	IEEE Micro
Volume	37
Issue number	3
DOIs	https://doi.org/10.1109/MM.2017.265090228
State	Published - May 2017

All Science Journal Classification (ASJC) codes

Software
Electrical and Electronic Engineering
Hardware and Architecture

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10.1109/MM.2017.265090228

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@article{e3c74f31247d40e8b612dddfe93c5f5d,

title = "TRANSISTENCY MODELS: MEMORY ORDERING AT THE HARDWARE–OS INTERFACE",

abstract = "THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM{\textquoteright}S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.",

author = "Daniel Lustig and Geet Sethi and Abhishek Bhattacharjee and Martonosi, \{Margaret Rose\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.",

year = "2017",

month = may,

doi = "10.1109/MM.2017.265090228",

language = "English (US)",

volume = "37",

pages = "88--97",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - TRANSISTENCY MODELS

T2 - MEMORY ORDERING AT THE HARDWARE–OS INTERFACE

AU - Lustig, Daniel

AU - Sethi, Geet

AU - Bhattacharjee, Abhishek

AU - Martonosi, Margaret Rose

PY - 2017/5

Y1 - 2017/5

N2 - THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM’S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.

AB - THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM’S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.

UR - https://www.scopus.com/pages/publications/85023640755

UR - https://www.scopus.com/inward/citedby.url?scp=85023640755&partnerID=8YFLogxK

U2 - 10.1109/MM.2017.265090228

DO - 10.1109/MM.2017.265090228

M3 - Article

AN - SCOPUS:85023640755

SN - 0272-1732

VL - 37

SP - 88

EP - 97

JO - IEEE Micro

JF - IEEE Micro

IS - 3

ER -

TRANSISTENCY MODELS: MEMORY ORDERING AT THE HARDWARE–OS INTERFACE

Abstract

All Science Journal Classification (ASJC) codes

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