TY - JOUR
T1 - TRANSISTENCY MODELS
T2 - MEMORY ORDERING AT THE HARDWARE–OS INTERFACE
AU - Lustig, Daniel
AU - Sethi, Geet
AU - Bhattacharjee, Abhishek
AU - Martonosi, Margaret Rose
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5
Y1 - 2017/5
N2 - THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM’S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.
AB - THIS ARTICLE INTRODUCES THE TRANSISTENCY MODEL, A SET OF MEMORY ORDERING RULES AT THE INTERSECTION OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION AND MEMORY CONSISTENCY MODELS. USING THEIR COATCHECK TOOL, THE AUTHORS SHOW HOW TO RIGOROUSLY MODEL, ANALYZE, AND VERIFY THE CORRECTNESS OF A GIVEN SYSTEM’S MICROARCHITECTURE AND SOFTWARE STACK WITH RESPECT TO ITS TRANSISTENCY MODEL SPECIFICATION.
UR - http://www.scopus.com/inward/record.url?scp=85023640755&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85023640755&partnerID=8YFLogxK
U2 - 10.1109/MM.2017.265090228
DO - 10.1109/MM.2017.265090228
M3 - Article
AN - SCOPUS:85023640755
SN - 0272-1732
VL - 37
SP - 88
EP - 97
JO - IEEE Micro
JF - IEEE Micro
IS - 3
ER -