Transistency Models: Memory Ordering at the Hardware-OS Interface

Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Rose Martonosi

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

This article introduces the transistency model, a set of memory ordering rules at the intersection of virtual-to-physical address translation and memory consistency models. Using their COATCheck tool, the authors show how to rigorously model, analyze, and verify the correctness of a given system's microarchitecture and software stack with respect to its transistency model specification.

Original languageEnglish (US)
Article number7948679
Pages (from-to)88-97
Number of pages10
JournalIEEE Micro
Volume37
Issue number3
DOIs
StatePublished - Jan 1 2017

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • COATCheck
  • Hardware-software
  • Transistency model
  • formal verification
  • memory consistency
  • memory ordering
  • modeling

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