Transistency Models: Memory Ordering at the Hardware-OS Interface

Daniel Lustig; Geet Sethi; Abhishek Bhattacharjee; Margaret Rose Martonosi

doi:10.1109/MM.2017.69

Transistency Models: Memory Ordering at the Hardware-OS Interface

Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Rose Martonosi

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

This article introduces the transistency model, a set of memory ordering rules at the intersection of virtual-to-physical address translation and memory consistency models. Using their COATCheck tool, the authors show how to rigorously model, analyze, and verify the correctness of a given system's microarchitecture and software stack with respect to its transistency model specification.

Original language	English (US)
Article number	7948679
Pages (from-to)	88-97
Number of pages	10
Journal	IEEE Micro
Volume	37
Issue number	3
DOIs	https://doi.org/10.1109/MM.2017.69
State	Published - 2017

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Keywords

COATCheck
Hardware-software
Transistency model
formal verification
memory consistency
memory ordering
modeling

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10.1109/MM.2017.69

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abstract = "This article introduces the transistency model, a set of memory ordering rules at the intersection of virtual-to-physical address translation and memory consistency models. Using their COATCheck tool, the authors show how to rigorously model, analyze, and verify the correctness of a given system's microarchitecture and software stack with respect to its transistency model specification.",

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author = "Daniel Lustig and Geet Sethi and Abhishek Bhattacharjee and Martonosi, {Margaret Rose}",

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Transistency Models: Memory Ordering at the Hardware-OS Interface

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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