Toward ideal on-chip communication using express virtual channels

Amit Kumar; Li Shiuan Peh; Partha Kundu; Niraj K. Jha

doi:10.1109/MM.2008.18

Toward ideal on-chip communication using express virtual channels

Amit Kumar, Li Shiuan Peh, Partha Kundu, Niraj K. Jha

Research output: Contribution to journal › Article › peer-review

78 Scopus citations

Abstract

Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

Original language	English (US)
Pages (from-to)	80-90
Number of pages	11
Journal	IEEE Micro
Volume	28
Issue number	1
DOIs	https://doi.org/10.1109/MM.2008.18
State	Published - Jan 2008

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Keywords

Flow control
On-chip interconnects
Packet switching
Router design

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10.1109/MM.2008.18

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title = "Toward ideal on-chip communication using express virtual channels",

abstract = "Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.",

keywords = "Flow control, On-chip interconnects, Packet switching, Router design",

author = "Amit Kumar and Peh, {Li Shiuan} and Partha Kundu and Jha, {Niraj K.}",

note = "Funding Information: We thank William J. Dally of Stanford University for useful feedback on this work. We also thank Ted Tabe and David V. James of Intel for their help with the modeling infrastructure and their comments on the microarchitecture. This work was supported in part by the MARCO Gigascale Systems Research Center, the Alfred P. Sloan Research Foundation, a grant from Intel, an Intel PhD fellowship, and NSF grants CNS-0613074 and CPA-0702110.",

year = "2008",

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AU - Kumar, Amit

AU - Peh, Li Shiuan

AU - Kundu, Partha

AU - Jha, Niraj K.

N1 - Funding Information: We thank William J. Dally of Stanford University for useful feedback on this work. We also thank Ted Tabe and David V. James of Intel for their help with the modeling infrastructure and their comments on the microarchitecture. This work was supported in part by the MARCO Gigascale Systems Research Center, the Alfred P. Sloan Research Foundation, a grant from Intel, an Intel PhD fellowship, and NSF grants CNS-0613074 and CPA-0702110.

PY - 2008/1

Y1 - 2008/1

N2 - Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

AB - Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

KW - Flow control

KW - On-chip interconnects

KW - Packet switching

KW - Router design

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JF - IEEE Micro

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Toward ideal on-chip communication using express virtual channels

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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