Abstract
This work demonstrates that under a given set of assumptions, transition tours on test models can be used for complete validation of an implementation against a specification, for a large and important class of designs that includes many programmable/hardwired, general-purpose processors/DSPs. A by-product of this study is specific guidelines for deriving the test model. Finally, the methodology is illustrated by applying it on a pipelined implementation of the DLX processor.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 740-745 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| DOIs | |
| State | Published - 1997 |
| Event | Proceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA Duration: Jun 9 1997 → Jun 13 1997 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Control and Systems Engineering