TOTALLY SELF-CHECKING MOS CIRCUITS UNDER REALISTIC PHYSICAL FAILURES.

A new approach is presented to implement totally self-checking (TSC) circuits in nMOS and Domino-CMOS technolgies. Existing realizations of the TSC circuits are at the logic gatelevel based on stuck-at faults. The implementations are made TSC with repsect to realistic physical failures. It is shown how self-checking gate-level designs can be implemented in these technologies so that the same set of input codewords is sufficient to detect stuck-gate faults of transistors in the MOS implementation. Many of the other device and interconnect failures are shown to be mapped to stuck-at faults or stuck-open faults. Conditions and layout rules are given for the detection of those failures which cannot be mapped, notably some diffusion and metal shorts. The fault-secure and code-disjoint properties are also investigated with respect to these physical failures.