Totally self-checking (TSC) circuits are a class of circuits which are used to detect errors concurrently with normal operation. They map encoded inputs to encoded outputs, which are monitored by checkers. In the presence of a fault in a TSC circuit at least one input codeword produces a noncode at the output (self-testing property), which is detected by the checker. The self-testing property is difficult to satisfy for TSC CMOS circuits, especially in the presence of timing skews in the input variables changes and unequal delays in the circuit. A new method for implementing TSC circuits in CMOS technology is presented. The method is guaranteed to be self-testing even under a dynamic behavior assumption (i. e. when arbitrary delays and timing skews are assumed).