TOTALLY SELF-CHECKING CMOS CIRCUITS USING A HYBRID REALIZATION.

Niraj Kumar Jha, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Totally self-checking (TSC) circuits are a class of circuits which are used to detect errors concurrently with normal operation. They map encoded inputs to encoded outputs, which are monitored by checkers. In the presence of a fault in a TSC circuit at least one input codeword produces a noncode at the output (self-testing property), which is detected by the checker. The self-testing property is difficult to satisfy for TSC CMOS circuits, especially in the presence of timing skews in the input variables changes and unequal delays in the circuit. A new method for implementing TSC circuits in CMOS technology is presented. The method is guaranteed to be self-testing even under a dynamic behavior assumption (i. e. when arbitrary delays and timing skews are assumed).

Original languageEnglish (US)
Title of host publicationDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
PublisherIEEE
Pages154-158
Number of pages5
ISBN (Print)0818606185
StatePublished - Dec 1 1985
Externally publishedYes

Publication series

NameDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
ISSN (Print)0731-3071

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'TOTALLY SELF-CHECKING CMOS CIRCUITS USING A HYBRID REALIZATION.'. Together they form a unique fingerprint.

  • Cite this

    Jha, N. K., & Abraham, J. A. (1985). TOTALLY SELF-CHECKING CMOS CIRCUITS USING A HYBRID REALIZATION. In Digest of Papers - FTCS (Fault-Tolerant Computing Symposium) (pp. 154-158). (Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)). IEEE.