Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility

Yifei Huang; Bahman Hekmatshoar; Sigurd Wagner; James C. Sturm

doi:10.1109/LED.2008.2000645

Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility

Yifei Huang, Bahman Hekmatshoar, Sigurd Wagner, James C. Sturm

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm²/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 10⁶. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.

Original language	English (US)
Pages (from-to)	737-739
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	29
Issue number	7
DOIs	https://doi.org/10.1109/LED.2008.2000645
State	Published - Jul 2008

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Keywords

Amorphous silicon
Amorphous silicon (α-Si)
Self-aligned silicide
Silicon
Thin-film transistor (TFT)
Top gate

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10.1109/LED.2008.2000645

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title = "Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility",

abstract = "We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.",

keywords = "Amorphous silicon, Amorphous silicon (α-Si), Self-aligned silicide, Silicon, Thin-film transistor (TFT), Top gate",

author = "Yifei Huang and Bahman Hekmatshoar and Sigurd Wagner and Sturm, {James C.}",

note = "Funding Information: Manuscript received January 14, 2008. This work was supported by the U.S. Display Consortium. The review of this letter was arranged by Editor J. Sin. The authors are with the Princeton Institute for the Science and Technology of Materials, Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: yhtwo@princeton.edu). Digital Object Identifier 10.1109/LED.2008.2000645 Fig. 1. Illustration of fabrication process: (a) Deposition of TFT stack (α-Si, gate dielectric, and gate metal); (b) definition of gate electrode; (c) definition of the channel width and electrical isolation of devices; (d) blanket deposition of Ni; (e) liftoff and silicidation; and (f) selective removal of unreacted Ni.",

year = "2008",

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doi = "10.1109/LED.2008.2000645",

language = "English (US)",

volume = "29",

pages = "737--739",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility

AU - Huang, Yifei

AU - Hekmatshoar, Bahman

AU - Wagner, Sigurd

AU - Sturm, James C.

N1 - Funding Information: Manuscript received January 14, 2008. This work was supported by the U.S. Display Consortium. The review of this letter was arranged by Editor J. Sin. The authors are with the Princeton Institute for the Science and Technology of Materials, Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: yhtwo@princeton.edu). Digital Object Identifier 10.1109/LED.2008.2000645 Fig. 1. Illustration of fabrication process: (a) Deposition of TFT stack (α-Si, gate dielectric, and gate metal); (b) definition of gate electrode; (c) definition of the channel width and electrical isolation of devices; (d) blanket deposition of Ni; (e) liftoff and silicidation; and (f) selective removal of unreacted Ni.

PY - 2008/7

Y1 - 2008/7

N2 - We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.

AB - We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.

KW - Amorphous silicon

KW - Amorphous silicon (α-Si)

KW - Self-aligned silicide

KW - Silicon

KW - Thin-film transistor (TFT)

KW - Top gate

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 7

ER -

Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility

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