Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility

Yifei Huang, Bahman Hekmatshoar, Sigurd Wagner, James Christopher Sturm

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.

Original languageEnglish (US)
Pages (from-to)737-739
Number of pages3
JournalIEEE Electron Device Letters
Volume29
Issue number7
DOIs
StatePublished - Jul 1 2008

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Keywords

  • Amorphous silicon
  • Amorphous silicon (α-Si)
  • Self-aligned silicide
  • Silicon
  • Thin-film transistor (TFT)
  • Top gate

Fingerprint Dive into the research topics of 'Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility'. Together they form a unique fingerprint.

  • Cite this