TY - JOUR
T1 - Top-gate amorphous silicon TFT with self-aligned silicide source/drain and high mobility
AU - Huang, Yifei
AU - Hekmatshoar, Bahman
AU - Wagner, Sigurd
AU - Sturm, James C.
N1 - Funding Information:
Manuscript received January 14, 2008. This work was supported by the U.S. Display Consortium. The review of this letter was arranged by Editor J. Sin. The authors are with the Princeton Institute for the Science and Technology of Materials, Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/LED.2008.2000645 Fig. 1. Illustration of fabrication process: (a) Deposition of TFT stack (α-Si, gate dielectric, and gate metal); (b) definition of gate electrode; (c) definition of the channel width and electrical isolation of devices; (d) blanket deposition of Ni; (e) liftoff and silicidation; and (f) selective removal of unreacted Ni.
PY - 2008/7
Y1 - 2008/7
N2 - We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.
AB - We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 °C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm2/V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 106. These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use.
KW - Amorphous silicon
KW - Amorphous silicon (α-Si)
KW - Self-aligned silicide
KW - Silicon
KW - Thin-film transistor (TFT)
KW - Top gate
UR - http://www.scopus.com/inward/record.url?scp=47249132138&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47249132138&partnerID=8YFLogxK
U2 - 10.1109/LED.2008.2000645
DO - 10.1109/LED.2008.2000645
M3 - Article
AN - SCOPUS:47249132138
SN - 0741-3106
VL - 29
SP - 737
EP - 739
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 7
ER -