TIMING ANALYSIS AND DESIGN OPTIMIZATION OF VLSI DATA FLOW ARRAYS.

S. Y. Kung, S. C. Lo, P. S. Lewis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Motivated primarily by their potential VLSI implementation, systolic and wavefront arrays have recently attracted significant research interest. A critical research topic is to formalize and systemize the design of such arrays directly from algorithm descriptions. Signal flow graphs (SFGs) provide a popular description for recursive parallel algorithms used in digital signal processing. A data flow graph (DFG) is used here as an abstract model for wavefront array processors, and the issue of transforming a SFG into a DFT by an equivalence transformation is addressed. The timing analysis for generalized (cyclic or acyclic) DFG networks is then discussed. Finally, an outline is given of algorithms for assigning a minimal number of queues required on all the edges of the DFG to achieve the best possible throughput rate. As a side-product of the timing analysis theorem, the deadlock problem associated with the DFG is resolved naturally.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsKai Hwang, Steven M. Jacobs, Earl E. Swartzlander
PublisherIEEE
Pages600-607
Number of pages8
ISBN (Print)0818607246
StatePublished - Dec 1 1986
Externally publishedYes

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Kung, S. Y., Lo, S. C., & Lewis, P. S. (1986). TIMING ANALYSIS AND DESIGN OPTIMIZATION OF VLSI DATA FLOW ARRAYS. In K. Hwang, S. M. Jacobs, & E. E. Swartzlander (Eds.), Proceedings of the International Conference on Parallel Processing (pp. 600-607). (Proceedings of the International Conference on Parallel Processing). IEEE.