@inproceedings{4a8c309190eb4df188ed34a2baab6332,
title = "TIMING ANALYSIS AND DESIGN OPTIMIZATION OF VLSI DATA FLOW ARRAYS.",
abstract = "Motivated primarily by their potential VLSI implementation, systolic and wavefront arrays have recently attracted significant research interest. A critical research topic is to formalize and systemize the design of such arrays directly from algorithm descriptions. Signal flow graphs (SFGs) provide a popular description for recursive parallel algorithms used in digital signal processing. A data flow graph (DFG) is used here as an abstract model for wavefront array processors, and the issue of transforming a SFG into a DFT by an equivalence transformation is addressed. The timing analysis for generalized (cyclic or acyclic) DFG networks is then discussed. Finally, an outline is given of algorithms for assigning a minimal number of queues required on all the edges of the DFG to achieve the best possible throughput rate. As a side-product of the timing analysis theorem, the deadlock problem associated with the DFG is resolved naturally.",
author = "Kung, {S. Y.} and Lo, {S. C.} and Lewis, {P. S.}",
year = "1986",
language = "English (US)",
isbn = "0818607246",
series = "Proceedings of the International Conference on Parallel Processing",
publisher = "IEEE",
pages = "600--607",
editor = "Kai Hwang and Jacobs, {Steven M.} and Swartzlander, {Earl E.}",
booktitle = "Proceedings of the International Conference on Parallel Processing",
}