@inproceedings{d22919b94d254b15be146666d680f1f6,
title = "TILE64{\texttrademark} processor: A 64-core SoC with mesh interconnect",
abstract = "An SoC with 64 tiles connected by mesh networks for networking and multimedia markets is fabricated in 90nm CMOS. Each tile consists of a processor with a 3-way VLIW execution pipeline, memory management, cache, and a switch to manage communication to and from five independent on-chip networks. The chip provides up to 384GOPS with 240GB/S of on-chip bisectional bandwidth.",
author = "Shane Bell and Bruce Edwards and John Amann and Rich Conlin and Kevin Joyce and Vince Leung and John MacKay and Mike Reif and Liewei Bao and John Brown and Matthew Mattina and Miao, \{Chyi Chang\} and Carl Ramey and David Wentzlaff and Walker Anderson and Ethan Berger and Nat Fairbanks and Durlov Khan and Froilan Montenegro and Jay Stickney and John Zook",
year = "2008",
doi = "10.1109/ISSCC.2008.4523070",
language = "English (US)",
isbn = "9781424420100",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "87--89",
booktitle = "2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC",
address = "United States",
note = "2008 IEEE International Solid State Circuits Conference, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
}