TILE64™ processor: A 64-core SoC with mesh interconnect

Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay StickneyJohn Zook

Research output: Chapter in Book/Report/Conference proceedingConference contribution

506 Scopus citations


An SoC with 64 tiles connected by mesh networks for networking and multimedia markets is fabricated in 90nm CMOS. Each tile consists of a processor with a 3-way VLIW execution pipeline, memory management, cache, and a switch to manage communication to and from five independent on-chip networks. The chip provides up to 384GOPS with 240GB/S of on-chip bisectional bandwidth.

Original languageEnglish (US)
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages3
ISBN (Print)9781424420100
StatePublished - 2008
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 3 2008Feb 7 2008

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530


Other2008 IEEE International Solid State Circuits Conference, ISSCC
Country/TerritoryUnited States
CitySan Francisco, CA

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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