Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

Rui Zhang, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


Many nanometer-scale devices have been proposed and fabricated recently. Several can implement threshold and majority logic efficiently. Research has also begun on design methodologies to keep pace with the development of these devices. Specifically, a threshold logic synthesis tool (TELS) and a majority/minority logic synthesis tool (MALS) have been developed recently. In this paper, we discuss several factorization methods to enhance the efficacy of these two tools significantly. We then augment the design methodology to allow the tools to produce totally self-checking (TSC) circuits which can efficiently implement concurrent error detection. Such circuits can be used to detect run-time errors. Two schemes are used to synthesize TSC circuits - one based on the Berger code and the other on the parity code. We compare and contrast these two schemes. Experimental results establish the effectiveness of the proposed approaches.

Original languageEnglish (US)
Title of host publicationGLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages6
ISBN (Print)1595933476, 9781595933478
StatePublished - 2006
EventGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States
Duration: Apr 30 2006May 2 2006

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


OtherGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
Country/TerritoryUnited States
CityPhiladelphia, PA

All Science Journal Classification (ASJC) codes

  • General Engineering


  • Design Algorithms


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