We found threshold voltage sensitivity to silicon thickness variation in 0.1 µm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.
|Original language||English (US)|
|Number of pages||3|
|Journal||IEEE Transactions on Electron Devices|
|State||Published - Sep 1995|
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering