Threshold Voltage Sensitivity of 0.1 µm Channel Length Fully-Depleted SOI NMOSFET's with Back-Gate Bias

Effendi Leobandung; Stephen Y. Chou

doi:10.1109/16.405292

Threshold Voltage Sensitivity of 0.1 µm Channel Length Fully-Depleted SOI NMOSFET's with Back-Gate Bias

Effendi Leobandung, Stephen Y. Chou

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

We found threshold voltage sensitivity to silicon thickness variation in 0.1 µm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.

Original language	English (US)
Pages (from-to)	1707-1709
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	42
Issue number	9
DOIs	https://doi.org/10.1109/16.405292
State	Published - Sep 1995
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/16.405292

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title = "Threshold Voltage Sensitivity of 0.1 µm Channel Length Fully-Depleted SOI NMOSFET's with Back-Gate Bias",

abstract = "We found threshold voltage sensitivity to silicon thickness variation in 0.1 µm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.",

author = "Effendi Leobandung and Chou, {Stephen Y.}",

note = "Funding Information: Manuscript received January 5, 1995; revised April 28, 1995. The review of this brief was arranged by Associate Editor K. Shenai. This work was supported in part by SRC under Contract 92-SJ-231 and NSF. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9413288.",

year = "1995",

month = sep,

doi = "10.1109/16.405292",

language = "English (US)",

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pages = "1707--1709",

journal = "IEEE Transactions on Electron Devices",

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T1 - Threshold Voltage Sensitivity of 0.1 µm Channel Length Fully-Depleted SOI NMOSFET's with Back-Gate Bias

AU - Leobandung, Effendi

AU - Chou, Stephen Y.

N1 - Funding Information: Manuscript received January 5, 1995; revised April 28, 1995. The review of this brief was arranged by Associate Editor K. Shenai. This work was supported in part by SRC under Contract 92-SJ-231 and NSF. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9413288.

PY - 1995/9

Y1 - 1995/9

N2 - We found threshold voltage sensitivity to silicon thickness variation in 0.1 µm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.

AB - We found threshold voltage sensitivity to silicon thickness variation in 0.1 µm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

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ER -

Threshold Voltage Sensitivity of 0.1 µm Channel Length Fully-Depleted SOI NMOSFET's with Back-Gate Bias

Abstract

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