Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects

In modern circuits, interconnect efficiency is a central determinant of circuit efficiency. Moreover, as technology is scaled down, the importance of efficient interconnect design is increasing. In this paper, we explore an option for lowpower interconnect synthesis at the 32nm node and beyond, using fin-type field-effect transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a previously-unexplored mechanism for improving FinFET efficiency, called threshold voltage control through multiple supply voltages (TCMS), which is significantly different from conventional multiple-supply voltage schemes. We develop a circuit design for a FinFET buffer using TCMS. We describe a variation of van Ginneken's classic dynamic programming framework for solving the problem of power-optimal TCMS buffer insertion on a given routing tree. We show that, on an average, TCMS can provide power savings of 50.41% and device area savings of 9.17% compared to a state-of-the-art dual-Vdd interconnect synthesis scheme1.