Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

Abhishek Bhattacharjee, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

123 Scopus citations

Abstract

With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boil down to discerning which running threads or processes are critical, or slowest, versus which are non-critical. If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. Possibilities include running the critical thread at a faster clock rate, performing load balancing techniques to offload work onto currently non-critical threads, or giving the critical thread more on-chip resources to execute faster. This paper proposes and evaluates simple but effective thread criticality predictors for parallel applications. We show that accurate predictors can be built using counters that are typically already available on-chip. Our predictor, based on memory hierarchy statistics, identifies thread crit-icality with an average accuracy of 93% across a range of architectures. We also demonstrate two applications of our predictor. First, we show how Intel's Threading Building Blocks (TBB) parallel runtime system can benefit from task stealing techniques that use our criticality predictor to reduce load imbalance. Using criticality prediction to guide TBB's task-stealing decisions improves performance by 13-32% for TBB-based PARSEC benchmarks running on a 32-core CMP. As a second application, criticality prediction guides dynamic energy optimizations in barrier-based applications. By running the predicted critical thread at the full clock rate and frequency-scaling non-critical threads, this approach achieves average energy savings of 15% while negligibly degrading performance for SPLASH-2 and PARSEC benchmarks.

Original languageEnglish (US)
Title of host publicationISCA 2009 - 36th Annual International Symposium on Computer Architecture, Conference Proceedings
Pages290-301
Number of pages12
DOIs
StatePublished - Nov 30 2009
EventISCA 2009 - 36th Annual International Symposium on Computer Architecture - Austin, TX, United States
Duration: Jun 20 2009Jun 24 2009

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

OtherISCA 2009 - 36th Annual International Symposium on Computer Architecture
CountryUnited States
CityAustin, TX
Period6/20/096/24/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Caches
  • DVFS
  • Intel TBB
  • Parallel processing
  • Thread criticality prediction

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    Bhattacharjee, A., & Martonosi, M. R. (2009). Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. In ISCA 2009 - 36th Annual International Symposium on Computer Architecture, Conference Proceedings (pp. 290-301). (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1145/1555754.1555792