The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply by using the dependence graph and cut-set procedure developed by Kung. This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique may be applied to ripple- through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.
|Original language||English (US)|
|Number of pages||7|
|Journal||IEEE Transactions on Acoustics, Speech, and Signal Processing|
|State||Published - May 1990|
All Science Journal Classification (ASJC) codes
- Signal Processing