The Use of Data Dependence Graphs in the Design of Bit-Level Systolic Arrays

John V. Mccanny, John G. McWhirter, Sun Yuan Kung

Research output: Contribution to journalArticlepeer-review

24 Scopus citations


The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply by using the dependence graph and cut-set procedure developed by Kung. This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique may be applied to ripple- through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.

Original languageEnglish (US)
Pages (from-to)787-793
Number of pages7
JournalIEEE Transactions on Acoustics, Speech, and Signal Processing
Issue number5
StatePublished - May 1990

All Science Journal Classification (ASJC) codes

  • Signal Processing


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