The performance advantages of integrating block data transfer in cache-coherent multiprocessors

Steven Cameron Woo, Jaswinder Pal Singh, John L. Hennessy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Integrating support for block data transfer has become an important emphasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that the benefits of block transfer are not substantial for hardware cachecoherent multiprocessors. The main reasons for this are (i) the relatively modest fraction of time applications spend in communication amenable to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains after block transfer, and (iii) long cache lines often capture many of the benefits of block transfer in efficient cache-coherent machines. In the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. We also examine the impact of varying important communication parameters and processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for real applications.

Original languageEnglish (US)
Title of host publicationProceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994
PublisherAssociation for Computing Machinery
Pages219-229
Number of pages11
ISBN (Electronic)0897916603
DOIs
StatePublished - Nov 1 1994
Externally publishedYes
Event6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994 - San Jose, United States
Duration: Oct 4 1994Oct 7 1994

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
VolumePart F129531

Other

Other6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994
CountryUnited States
CitySan Jose
Period10/4/9410/7/94

All Science Journal Classification (ASJC) codes

  • Software
  • Information Systems
  • Hardware and Architecture

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    Woo, S. C., Singh, J. P., & Hennessy, J. L. (1994). The performance advantages of integrating block data transfer in cache-coherent multiprocessors. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 1994 (pp. 219-229). (International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS; Vol. Part F129531). Association for Computing Machinery. https://doi.org/10.1145/195473.195547