The Design of Dynamically Reconfigurable Datapath Coprocessors

Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo

Research output: Contribution to journalArticle

25 Scopus citations

Abstract

Increasing nonrecurring engineering and mask costs are making it harder to turn to hardwired application specific integrated circuit (ASIC) solutions for high-performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium-volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space-a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating coprocessor. This datapath consists of hardwired function units and reconfigurable interconnect.We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application-specific platforms.

Original languageEnglish (US)
Pages (from-to)361-384
Number of pages24
JournalACM Transactions on Embedded Computing Systems
Volume3
Issue number2
DOIs
StatePublished - May 1 2004

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Keywords

  • Algorithm
  • Design
  • Loop pipelining
  • Performance
  • coarse-grain reconfigurable fabric
  • datapath synthesis
  • interconnection design
  • reconfigurable datapath

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