TY - GEN
T1 - The accelerator wall
T2 - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019
AU - Fuchs, Adi
AU - Wentzlaff, David
N1 - Funding Information:
We thank Niraj Jha, Ruby Lee, Margaret Martonosi, Prateek Mittal, Mohammad Shahrad, and the anonymous reviewers for their useful feedback. This material is based on research sponsored by the NSF under Grants No. CNS-1823222 and CCF-1453112, Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement No. FA8650-18-2-7846, FA8650-18-2-7852, and FA8650-18-2-7862. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA), the NSF, or the U.S. Government.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/3/26
Y1 - 2019/3/26
N2 - Specializing chips using hardware accelerators has become the prime means to alleviate the gap between the growing computational demands and the stagnating transistor budgets caused by the slowdown of CMOS scaling. Much of the benefits of chip specialization stems from optimizing a computational problem within a given chip's transistor budget. Unfortunately, the stagnation of the number of transistors available on a chip will limit the accelerator design optimization space, leading to diminishing specialization returns, ultimately hitting an accelerator wall. In this work, we tackle the question of what are the limits of future accelerators and chip specialization? We do this by characterizing how current accelerators depend on CMOS scaling, based on a physical modeling tool that we constructed using datasheets of thousands of chips. We identify key concepts used in chip specialization, and explore case studies to understand how specialization has progressed over time in different applications and chip platforms (e.g., GPUs, FPGAs, ASICs)1. Utilizing these insights, we build a model which projects forward to see what future gains can and cannot be enabled from chip specialization. A quantitative analysis of specialization returns and technological boundaries is critical to help researchers understand the limits of accelerators and develop methods to surmount them.
AB - Specializing chips using hardware accelerators has become the prime means to alleviate the gap between the growing computational demands and the stagnating transistor budgets caused by the slowdown of CMOS scaling. Much of the benefits of chip specialization stems from optimizing a computational problem within a given chip's transistor budget. Unfortunately, the stagnation of the number of transistors available on a chip will limit the accelerator design optimization space, leading to diminishing specialization returns, ultimately hitting an accelerator wall. In this work, we tackle the question of what are the limits of future accelerators and chip specialization? We do this by characterizing how current accelerators depend on CMOS scaling, based on a physical modeling tool that we constructed using datasheets of thousands of chips. We identify key concepts used in chip specialization, and explore case studies to understand how specialization has progressed over time in different applications and chip platforms (e.g., GPUs, FPGAs, ASICs)1. Utilizing these insights, we build a model which projects forward to see what future gains can and cannot be enabled from chip specialization. A quantitative analysis of specialization returns and technological boundaries is critical to help researchers understand the limits of accelerators and develop methods to surmount them.
KW - Accelerator Wall
KW - CMOS Scaling
KW - Moore's Law
UR - http://www.scopus.com/inward/record.url?scp=85064230956&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85064230956&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2019.00023
DO - 10.1109/HPCA.2019.00023
M3 - Conference contribution
AN - SCOPUS:85064230956
T3 - Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019
SP - 1
EP - 14
BT - Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 16 February 2019 through 20 February 2019
ER -