Testing of Zipper CMOS Logic Circuits

Oiao Tong, Niraj K. Jha

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

Dynamic CMOS circuits are known to have area and speed advantages over static CMOS circuits. Zipper CMOS is a dynamic CMOS circuit technique which also provides protection against instability and charge-sharing problems. This is achieved by using a special driver circuit. In this paper we present a method for testing of zipper CMOS circuits. We first derive a gate-level model for the circuit and then obtain a single stuck-at fault test set for the model. We rearrange and possibly repeat some vectors in the test set so that it can be used to detect single stuck-open and stuck-on faults in addition to stuck-at faults in the zipper CMOS circuit. We also consider faults in the driver circuit.

Original languageEnglish (US)
Pages (from-to)877-880
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number3
DOIs
StatePublished - Jun 1990

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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