Testing of zipper CMOS logic circuits

Qiao Tong, Niraj K. Jha

Research output: Contribution to journalConference article

Abstract

A method for testing zipper CMOS circuits is presented. A gate-level model for the circuit is derived, and a single stuck-at fault test set for the model is obtained. Vectors are rearranged in the test set so that it can be used to detect single stuck-open and stuck-on faults in addition to stuck-at faults in the zipper CMOS circuit. Faults in the drive circuit are considered.

Original languageEnglish (US)
Pages (from-to)9-12
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Dec 1 1990
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Testing of zipper CMOS logic circuits'. Together they form a unique fingerprint.

  • Cite this