Testing for Multiple Faults in Domino-CMOS Logic Circuits

The problem of detecting multiple faults in domino-CMOS logic circuits is considered. The multiple faults can consist of faults of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to first initialize the domino-CMOS circuit. Then a multiple stuck-at fault test set based on the gate-level model of the circuit is applied. This results in the detection of all multiple faults, whose consistent faults are detectable. The problem of test set invalidation due to arbitrary signal delays can be easily taken care of in domino-CMOS circuits. This makes a domino-CMOS implementation of a function even more attractive than a fully complementary CMOS implementation from the testability point of view.