Testing Aspects of Nanotechnology Trends

Mehdi B. Tahoori, Niraj K. Jha, R. Iris Bahar

Research output: Chapter in Book/Report/Conference proceedingChapter


Emerging nanoscale devices will enable an extremely high density of components to be integrated onto a single substrate. This chapter reveals some of the most promising emerging nanoscale devices, namely resonant tunneling diodes (RTDs), quantum-dot cellular automata (QCA), carbon nanotubes/silicon nanowires, and carbon nanotube field effect transistors (CNFETs). It discusses some test challenges and presents test generation techniques for these devices. In particular, it discusses defect characterization, fault modeling, and test generation of circuits based on RTDs and QCA. It also describes built-in self-test (BIST) of carbon-nanotube-based crossbar array architectures and presents imperfection and variation tolerance in logic circuits implemented by CNFETs. It concludes with a discussion of future challenges and trends in nanoscale computing. Regardless of which devices make their way into the mainstream of nanoscale computing, there is a general consensus that testing will be a key issue, as these devices are expected to have high defect rates. Consequently, some sort of defect and fault tolerance schemes will have to be built into nanoscale circuits, systems, and architectures. Ultimately, the testability and reliability of these devices will need to become an additional constraint during system design.

Original languageEnglish (US)
Title of host publicationSystem-on-Chip Test Architectures
PublisherElsevier Inc.
Number of pages41
ISBN (Print)9780123739735
StatePublished - 2008

All Science Journal Classification (ASJC) codes

  • General Computer Science


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