TESTABLE CMOS LOGIC CIRCUITS UNDER DYNAMIC BEHAVIOR.

Niraj Kumar Jha, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Owing to the sequential behavior of CMOS logic circuits in the presence of a stuck-open fault, it is required that an initialization input followed by a test input be applied to detect such a fault. However, a test set generated under a static behavior assumption can be invalidated in the presence of time-skews in the variable changes and/or unequal delays in the different interconnections of the circuits. The authors present a necessary and sufficient condition for the existence of a test set that cannot be invalidated under dynamic behavior (variable delays assumed), for an AND-OR or OR-AND CMOS realization for any given function. They also introduce a hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under the assumption of dynamic behavior.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages131-133
Number of pages3
StatePublished - Dec 1 1984
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Jha, N. K., & Abraham, J. A. (1984). TESTABLE CMOS LOGIC CIRCUITS UNDER DYNAMIC BEHAVIOR. In Unknown Host Publication Title (pp. 131-133). IEEE.