TY - JOUR
T1 - Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques
AU - Lingappan, Loganathan
AU - Ravi, Srivaths
AU - Raghunathan, Anand
AU - Jha, Niraj K.
AU - Chakradhar, Srimat T.
N1 - Funding Information:
Dr. Jha is an Association for Computing Machinery (ACM) Fellow. He has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING. He is currently the Editor of IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, the Journal of Electronic Testing: Theory and Applications (JETTA), the Journal of Low Power Electronics, and the Journal of Embedded Computing. He has served as the Guest Editor for the JETTA special issue on high-level test synthesis. He has also served as the Program Chairman of the Workshop on Fault-Tolerant Parallel and Distributed Systems in 1992 and the International Conference on Embedded and Ubiquitous Computing in 2004. He is the recipient of the American Telephone and Telegraph Company (AT&T) Foundation Award and Nippon Electric Company (NEC) Preceptorship Award for research excellence, the National Cash Register (NCR) Company Award for teaching excellence, and the Princeton University Graduate Mentoring Award. He received the Best Paper Awards at the International Conference on Computer Design (ICCD) in 1993, the International Symposium on Fault-Tolerant Computing (FTCS) in 1997, the International Conference on VLSI Design (ICVLSID) in 1998, the Design Automation Conference (DAC) in 1999, the International Conference on Parallel and Distributed Computing and Systems (PDCS) in 2002, and the ICVLSID in 2003. One of his papers was also selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years.” Srimat T. Chakradhar (S’88–M’91) received the Ph.D. degree in computer science from Rutgers University, Piscataway, NJ, in 1990.
PY - 2006/10
Y1 - 2006/10
N2 - In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern systems-on-a-chip (SOC). Their techniques are based on the following observations: 1) Conventional test compression schemes, which are designed to satisfy various constraints including low hardware overheads and decompression times, cannot fully exploit compression opportunities present in test data and 2) due to the diversity of components used in SOCs (and consequently in their test strategies and test-data characteristics), a single compression strategy may not be best suited to handle them. The authors propose the use of multilevel and heterogeneous test compression schemes to address the above issues and demonstrate that they can provide significant reductions in the test volume above currently known state-of-the-art test compression techniques. An architecture that reuses infrastructure components already present in SOCs (programmable processors, on-chip communication architecture, memory, etc.) for an efficient implementation of their techniques is proposed. Finally, the authors suggest various architectural-customization techniques, such as partitioning of the decompression functionality between the hardware and software and the addition of custom instructions, to improve decompression times and reduce hardware overheads. Experiments with several designs, including an industrial media-processing SOC, demonstrate the efficacy of the proposed techniques in achieving test-data-volume reductions with low overheads.
AB - In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern systems-on-a-chip (SOC). Their techniques are based on the following observations: 1) Conventional test compression schemes, which are designed to satisfy various constraints including low hardware overheads and decompression times, cannot fully exploit compression opportunities present in test data and 2) due to the diversity of components used in SOCs (and consequently in their test strategies and test-data characteristics), a single compression strategy may not be best suited to handle them. The authors propose the use of multilevel and heterogeneous test compression schemes to address the above issues and demonstrate that they can provide significant reductions in the test volume above currently known state-of-the-art test compression techniques. An architecture that reuses infrastructure components already present in SOCs (programmable processors, on-chip communication architecture, memory, etc.) for an efficient implementation of their techniques is proposed. Finally, the authors suggest various architectural-customization techniques, such as partitioning of the decompression functionality between the hardware and software and the addition of custom instructions, to improve decompression times and reduce hardware overheads. Experiments with several designs, including an industrial media-processing SOC, demonstrate the efficacy of the proposed techniques in achieving test-data-volume reductions with low overheads.
KW - Data compression
KW - System-on-a-chip
KW - Test data
KW - Test volume
UR - http://www.scopus.com/inward/record.url?scp=33748290195&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748290195&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2005.862735
DO - 10.1109/TCAD.2005.862735
M3 - Article
AN - SCOPUS:33748290195
SN - 0278-0070
VL - 25
SP - 2193
EP - 2205
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 10
M1 - 1677701
ER -