Test synthesis of systems-on-a-chip

Srivaths Ravi, Niraj Kumar Jha

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

Embedded systems are increasingly synthesized today as systems-on-a-chip (SOCs), wherein existing functional blocks (also called cores) are used to implement different functions in the system specification. Emphasis during system synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a postprocessing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, performing test modifications after the SOC design has been optimized for target design constraints does not preserve the optimality of the solution obtained. In this paper, the authors present the first system-level synthesis for testability framework that integrates testability considerations into the synthesis process. Their work incorporates finite-state automata (FSA)-based symbolic testability analysis within the framework of an existing multiobjective optimization-based system synthesis tool to provide a viable solution. The experimental results show that the use of FSA-based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. Systems synthesis through the integrated framework for a number of examples indicates that efficient SOC architectures, which tradeoff different architectural features such as integrated circuit price, power consumption, and area under real-time constraints, can now be easily generated with low testability costs.

Original languageEnglish (US)
Pages (from-to)1211-1217
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume21
Issue number10
DOIs
StatePublished - Oct 1 2002

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Keywords

  • Design for testability
  • Synthesis for testability
  • System-on-a-chip
  • Test synthesis

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