Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha

Research output: Contribution to conferencePaperpeer-review

18 Scopus citations

Abstract

In this paper, we present a satisfiability-based algorithm for automatically generating test sequences that target gate-level stuck-at faults in a circuit by using its register-transfer level (RTL) description. Our methodology exploits a popular, unified RTL circuit representation, called assignment decision diagrams, for its analysis and justifies module-level pre-computed test vectors on this representation. Test generation proceeds by abstracting the components in this unified representation using input/output propagation rules, so that any justification/propagation event can be captured as a Boolean implication. Consequently, we reduce RTL test generation to a satisfiability (SAT) instance that has a significantly lower complexity than the equivalent problem at the gate-level. Using the state-of-the-art SAT solver ZCHAFF, we show that our RTL test generator can outperform gate-level sequential automatic test pattern generation (ATPG) in terms of both fault coverage and test generation, time (two-to-three orders of magnitude speed-up), in comparable test application times. Furthermore, we show that in a bi-level testing scenario, in which RTL ATPG is followed by gate-level sequential ATPG on the remaining faults, we improve the fault coverage even further, while maintaining a high speed-up in test generation time (nearly 29X) over pure gate-level sequential ATPG, at comparable test application times.

Original languageEnglish (US)
Pages187-193
Number of pages7
StatePublished - Dec 2 2003
EventProceedings: 21st International Conference on Computer Design ICCD 2003 - San Jose, CA, United States
Duration: Oct 13 2003Oct 15 2003

Other

OtherProceedings: 21st International Conference on Computer Design ICCD 2003
CountryUnited States
CitySan Jose, CA
Period10/13/0310/15/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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