Temperature-aware on-chip networks

Shang Li; Li Shiuan Peh; Amit Kumar; Niraj K. Jha

doi:10.1109/MM.2006.23

Temperature-aware on-chip networks

Shang Li, Li Shiuan Peh, Amit Kumar, Niraj K. Jha

Research output: Contribution to journal › Article › peer-review

28 Scopus citations

Abstract

On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. This thermal modeling and simulation framework combines with a distributed runtime scheme for thermal management to offer a path to thermally efficient on-chip network design.

Original language	English (US)
Pages (from-to)	130-139
Number of pages	10
Journal	IEEE Micro
Volume	26
Issue number	1
DOIs	https://doi.org/10.1109/MM.2006.23
State	Published - Jan 2006

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2006.23

Cite this

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title = "Temperature-aware on-chip networks",

abstract = "On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. This thermal modeling and simulation framework combines with a distributed runtime scheme for thermal management to offer a path to thermally efficient on-chip network design.",

author = "Shang Li and Peh, {Li Shiuan} and Amit Kumar and Jha, {Niraj K.}",

note = "Funding Information: This work was supported in part by Princeton University{\textquoteright}s Wallace Memorial Honorific Fellowship, the National Science Foundation under grant CCR-0237540 (CAREER) and CCR-0324891, and the Marco Gigascale Systems Research Center.",

year = "2006",

month = jan,

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T1 - Temperature-aware on-chip networks

AU - Li, Shang

AU - Peh, Li Shiuan

AU - Kumar, Amit

AU - Jha, Niraj K.

N1 - Funding Information: This work was supported in part by Princeton University’s Wallace Memorial Honorific Fellowship, the National Science Foundation under grant CCR-0237540 (CAREER) and CCR-0324891, and the Marco Gigascale Systems Research Center.

PY - 2006/1

Y1 - 2006/1

N2 - On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. This thermal modeling and simulation framework combines with a distributed runtime scheme for thermal management to offer a path to thermally efficient on-chip network design.

AB - On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. This thermal modeling and simulation framework combines with a distributed runtime scheme for thermal management to offer a path to thermally efficient on-chip network design.

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JO - IEEE Micro

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IS - 1

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Temperature-aware on-chip networks

Abstract

All Science Journal Classification (ASJC) codes

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