The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independentcircu it to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.
|Original language||English (US)|
|Title of host publication||Low-Power CMOS Design|
|Publisher||John Wiley and Sons Inc.|
|Number of pages||6|
|State||Published - Jan 1 1998|
All Science Journal Classification (ASJC) codes
- Computer Science(all)