Technology mapping for low power

Vivek Tiwari, Pranav Ashar, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independentcircu it to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

Original languageEnglish (US)
Title of host publicationLow-Power CMOS Design
PublisherJohn Wiley and Sons Inc.
Pages542-547
Number of pages6
ISBN (Electronic)9780470545058
ISBN (Print)9780780334298
DOIs
StatePublished - Jan 1 1998

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Computer Science(all)
  • Energy(all)

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    Tiwari, V., Ashar, P., & Malik, S. (1998). Technology mapping for low power. In Low-Power CMOS Design (pp. 542-547). John Wiley and Sons Inc.. https://doi.org/10.1109/9780470545058.sect14