Technology Mapping for low power

Vivek Tiwari, Pranav Ashar, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

68 Scopus citations


The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality-its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Number of pages6
ISBN (Print)0897915771
StatePublished - 1993
EventProceedings of the 30th ACM/IEEE Design Automation Conference - Dallas, TX, USA
Duration: Jun 14 1993Jun 18 1993

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123


OtherProceedings of the 30th ACM/IEEE Design Automation Conference
CityDallas, TX, USA

All Science Journal Classification (ASJC) codes

  • General Engineering


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